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| SL811HS SL811HS Embedded USB Host/Slave Controller Cypress Semiconductor Corporation Document #: 38-08008 Rev. *A * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised March 14, 2002 SL811HS TABLE OF CONTENTS 1.0 CONVENTIONS .............................................................................................................................. 4 2.0 DEFINITIONS .................................................................................................................................. 4 3.0 REFERENCES ................................................................................................................................ 4 4.0 INTRODUCTION ............................................................................................................................. 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Block Diagram ................................................................................................................................ 4 SL811HS Host or Slave Mode Selection [Master/Slave Mode] .................................................. 5 Features .......................................................................................................................................... 5 Data Port, Microprocessor Interface ............................................................................................ 6 Interrupt Controller ........................................................................................................................ 6 Buffer Memory ............................................................................................................................... 6 PLL Clock Generator ..................................................................................................................... 6 USB Transceiver ............................................................................................................................ 8 5.0 SL811HS REGISTERS ................................................................................................................... 8 5.1 Register Values on Power-up and Reset ..................................................................................... 9 5.2 USB Control Registers .................................................................................................................. 9 5.3 SL811HS Control Registers ........................................................................................................ 12 6.0 SL811HS AND SL811HST-AC PHYSICAL CONNECTIONS ...................................................... 16 6.1 SL811HS Physical Connections ................................................................................................. 16 6.2 SL811HST-AC Physical Connections ........................................................................................ 19 7.0 ELECTRICAL SPECIFICATIONS ................................................................................................. 22 7.1 7.2 7.3 7.4 7.5 7.6 Absolute Maximum Ratings ........................................................................................................ 22 Recommended Operating Condition ........................................................................................ 22 External Clock Input Characteristics (X1) ................................................................................. 22 DC Characteristics ....................................................................................................................... 23 USB Host Transceiver Characteristics ...................................................................................... 23 Bus Interface Timing Requirements .......................................................................................... 24 .............................................................................................................. 28 LIST OF FIGURES Figure 4-1. Figure 4-2. Figure 4-3. Figure 6-1. Figure 6-2. SL811HS USB Host/Slave Controller Functional Block Diagram ................................ 5 Full-Speed 48-MHz Crystal Circuit .................................................................................. 7 Optional 12-MHz Crystal Circuit ...................................................................................... 7 SL811HS USB Host/Slave Controller--Pin Layout ...................................................... 16 SL811HST-AC USB Host/Slave Controller Pin Layout ................................................ 19 LIST OF TABLES Table 6-1. SL811HS Pin Assignments and Definitions ................................................................... 17 Table 6-2. SL811HST-AC Pin Assignments and Definitions ........................................................... 20 8.0 PACKAGE DIAGRAMS Document #: 38-08008 Rev. *A Page 2 of 29 SL811HS License Agreement Use of this document and the intellectual properties contained herein indicates acceptance of the following License Agreement. If you do not accept the terms of this License Agreement, do not use this document, or the associated intellectual properties, or any other material you received in association with this product, and return this document and the associated materials within fifteen (15) days to Cypress Semiconductor Corporation or (CY) or CY's authorized distributor from whom you purchased the product. 1. You can only legally obtain CY's intellectual properties contained in this document through CY or its authorized distributors. 2. You are granted a nontransferable license to use and to incorporate CY's intellectual properties contained in this document into your product. The product may be either for your own use or for sale. 3. You may not reverse-engineer the SL811HS or otherwise attempt to discover the designs of SL811HS. 4. You may not assign, distribute, sell, transfer or disclose CY's intellectual properties contained in this document to any other person or entity. 5. This license terminates if you fail to comply with any of the provisions of this Agreement. You agree upon termination to destroy this document, stop using the intellectual properties contained in this document and any of its modification and incorporated or merged portions in any form, and destroy any unused SL811HS chips. Warranty Disclaimer and Limited Liability Cypress (CY), hereafter referred to as the manufacturer, warrants that its products substantially conform to its specifications for a period of ninety (90) days from delivery as evidenced by the shipment records. The manufacturer's sole obligation and liability for breaching the foregoing warranty shall be to replace or correct the defective products so that it substantially conforms to its specifications. Any modification of the products by anyone other than the manufacturer voids the foregoing warranty. No other warranties are expressed and none shall be implied. The manufacturer makes no warrant for the use of its products. In order to minimize risks associated with customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. The manufacturer's products are not designed, authorized, or warranted suitable for use in life-support devices or systems or other critical applications. The manufacturer specifically excludes any implied warranties of merchantability and fitness for a particular purpose unless prohibited by law. In no event shall the manufacturer's liability to you for damages hereunder for any cause whatsoever exceed the amount paid by you for the products. In no event will the manufacturer be liable for any loss of profits or other incidental or consequential damages arising out of the use or inability to use the product even if the manufacturer have been advised of the possibility of such damages. The manufacturer reserves the right to make changes at any time, without notice, to improve design or performance and supply the best product possible. The manufacturer assumes no responsibility for any errors that may appear in its technical document on the products nor does it make a commitment to update the information contained in its technical document. Nothing contained in the technical documents of the products shall be construed as a recommendation to use any products in violation of existing patents, copyrights or other rights of third parties. No license is granted by implication or otherwise under any patent, patent rights or other rights, of the manufacturer. Document #: 38-08008 Rev. *A Page 3 of 29 SL811HS 1.0 1,2,3,4 Dh, 1Fh, 39h 0101b, 010101b bRequest, n Conventions Numbers without annotations are decimals. Hexadecimal numbers are followed by an "h." Binary numbers are followed by a "b." Words in italics indicate terms defined by USB Specification or by this Specification. 2.0 USB SL811HS Definitions Universal Serial Bus The SL811HS is a Cypress USB Host/Slave Controller, providing multiple functions on a single chip. This part is offered in both a 28-pin PLCC package (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Throughout this document, "SL811HS" refers to both packages unless otherwise noted. Note: This chip does not include CPU. The SL11 is a Cypress USB Peripheral Device Controller, providing multiple functions on a single chip. This part is offered in both a 28-pin PLCC package (SL11) and a 48-pin TQFP package (SL11T-AC). Throughout this document, "SL11" refers to both packages unless otherwise noted. Note: This chip does not include a CPU. The SL11H is a Cypress USB Host/Slave Controller, providing multiple functions on a single chip. This part is offered in both a 28-Pin PLCC package (SL11H) and a 48-Pin TQFP package (SL11HT-AC). Throughout this document, "SL11H" refers to both packages unless otherwise noted. Note: This chip does not include CPU. Least Significant Bit Most Significant Bit Read/Write Phase Lock Loop Random Access Memory Serial Interface Engine Handshake packet indicates a positive acknowledgment. Handshake packet indicating a negative acknowledgment Universal Serial Bus Driver Start of Frame is the first transaction in each frame. It allows endpoints to identify the start of the frame and synchronize internal endpoint clocks to the host. Cyclic Redundancy Check The host computer system on which the USB Host Controller is installed SL11 SL11H LSB MSB R/W PLL RAM SIE ACK NAK USBD SOF CRC HOST 3.0 References [Ref 1] USB Specification 1.1: http://www.usb.org. 4.0 4.1 Introduction Block Diagram The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB peripherals. The SL811HS can interface to devices such as microprocessors, microcontrollers, DSPs, or directly to a variety of buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1. The SL811HS USB Host/Slave Controller incorporates USB Serial Interface functionality along with internal full-/low-speed transceivers. The SL811HS supports and operates in USB full-speed mode at 12 Mbps, or at low-speed 1.5-Mbps mode. The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support to allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUs and many others. Internally, the SL811HS contains a 256-byte RAM data buffer which is used for control registers and data buffer. The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages operate at 3.3 VDC. The I/O interface logic is 5V-tolerant. Document #: 38-08008 Rev. *A Page 4 of 29 SL811HS Master/Slave Controller INTERRUPT CONTROLLER RAM INTR D+ D- USB Root-HUB XCVRS SERIAL INTERFACE ENGINE BUFFERS & CONTROL REGISTERS PROCESSOR CLOCK GENERATOR INTERFACE nWR nRD nCS nRST D0-7 X1 X2 Figure 4-1. SL811HS USB Host/Slave Controller Functional Block Diagram 4.2 SL811HS Host or Slave Mode Selection [Master/Slave Mode] SL811HS can work in two modes--host or slave. For slave-mode operation and specification, please refer to the SL811S specification. This data sheet only covers host-mode operation. 4.3 Features * The only USB Host/Slave controller for embedded systems in the market with a standard microprocessor bus interface. * Supports both full-speed (12 Mbps) and low-speed (1.5 Mbps) USB transfer 4.3.1 USB Specification Compliance * Conforms to USB Specification 1.1 4.3.2 CPU Interface * Operates as a single USB host or slave under software control * Low-speed 1.5 Mbps, and full speed 12 Mbps, in both master and slave modes * Automatic detection of either low- or full-speed devices * 8-bit bidirectional data, port I/O (DMA supported in slave mode) * On-chip SIE and USB transceivers * On-chip single root HUB support * 256-byte internal SRAM buffer, ping-pong operation * Operates from 12- or 48-MHz crystal or oscillator (built-in DPLL) * 5 V-tolerant interface * Suspend/resume, wake up, and low-power modes are supported * Auto-generation of SOF and CRC5/16 * Auto-address increment mode, saves memory Read/Write cycles * Development kit including source code drivers is available * Backward-compatible with SL11H, both pin and functionality * 3.3V power source, 0.35 micron CMOS technology * Available in both a 28-pin PLCC package (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Document #: 38-08008 Rev. *A Page 5 of 29 SL811HS 4.4 Data Port, Microprocessor Interface The SL811HS microprocessor interface provides an 8-bit bidirectional data path along with appropriate control lines to interface to external processors or controllers. The control lines, Chip Select, Read and Write input strobes and a single address line, A0, along with the 8-bit data bus, support programmed I/O or memory mapped I/O designs. Access to memory and control register space is a simple two step process, requiring an address Write with A0 set = "0," followed by a register/memory Read or Write cycle with address line A0 set = "1." In addition, DMA bidirectional interface in slave mode is available with handshake signals such as DREQ, ACK, WR, RD, CS and INTR. Please refer to the SL811S spec. The SL811HS Write or Read operation terminates when either nWR or nCS goes inactive. For devices interfacing to the SL811HS, that deactivate the Chip Select nCS before the Write nWR, the data hold timing should be measured from the nCS and will be the same value as specified. Thus, both Intel- and Motorola-type CPUs can work easily with the SL811HS without any external glue logic requirements. 4.5 Interrupt Controller The SL811HS interrupt controller provides a single output signal (INTRQ) that can be activated by a number of events that may occur as result of USB activity. Control and status registers are provided to allow the user to select single or multiple events, which will generate an interrupt (assert INTRQ), and lets the user view interrupt status. The interrupts can be cleared by writing to the appropriate register (the Status Register at address 0x0d). 4.6 Buffer Memory The SL811HS contains 256 bytes of internal buffer memory. The first 16 bytes of memory represent control and status registers for programmed I/O operations. The remaining memory locations are used for data buffering (max. 240 Bytes). Access to the registers and data memory is through an external microprocessor, 8-bit data bus, in either of two addressing modes, indexed or, if used with multiplexed address/data bus interfaces, direct access. With indexed addressing, the address is first written to the device with the A0 address line LOW, then the following cycle with A0 address line HIGH is directed to the specified address. USB transactions are automatically routed to the memory buffer. Control registers are provided, so that pointers and block sizes in buffer memory can be can set up. 4.6.1 Auto Address Increment Mode The SL811HS supports auto-increment mode for Read or Write Cycles, A0 mode. In A0 mode, the Micro Controller sets up the address only once. On any subsequent DATA Read or Write access, the internal address pointer will advance to the next DATA location. 4.6.1.1 For example Write 0x10 to SL811HS in address cycle (A0 is set LOW) Write 0x55 to SL811HS in data cycle (A0 is set HIGH) -> Write 0x55 to location 0x10 Write 0xaa to SL811HS in data cycle (A0 is set HIGH) -> Write 0xaa to location 0x11 Write 0xbb to SL811HS in data cycle (A0 is set HIGH) -> Write 0xbb to location 0x12 The advantage of auto address increment mode is that it reduces the number of SL811HS memory Read/Write cycles required to move data to/from the device. For example, transferring 64-bytes of data to/from SL811HS using auto increment mode, will reduce the number of cycles to 1 Address Write and 64 Read/Write Data cycles, compared to 64 Address Writes and 64 Data Cycles for Random Access. 4.7 PLL Clock Generator Either a 12-MHz or a 48-MHz external crystal can be used with the SL811HS. Two pins, X1 and X2, are provided to connect a low-cost crystal circuit to the device as shown in Figure 4-2 and Figure 4-3. If an external 48-MHz clock source is available in the application, it can be used instead of the crystal circuit by connecting the source directly to the X1 input pin. When a clock is used, the X2 pin is left unconnected. Document #: 38-08008 Rev. *A Page 6 of 29 SL811HS X1 X2 Rf 1M Rs X1 48 MHz, series, 20-pF load 100 Cbk 0.01 F Cout 22 pF Cin 22 pF Lin 2.2 H Figure 4-2. Full-Speed 48-MHz Crystal Circuit X1 X2 Rf 1M Rs 100 X1 12 MHz , series, 20-pF load Cin 22 pF Cout 22 pF Figure 4-3. Optional 12-MHz Crystal Circuit Note: 1. CM (Clock Mode) pin of the SL811HS should be tied to GND when 48-MHz Xtal circuit or 48-MHz clock source is used. Document #: 38-08008 Rev. *A Page 7 of 29 SL811HS 4.7.1 Typical Crystal Requirements The following are examples of "typical requirements". Please note that these specifications are generally found as standard crystal values and are therefore less expensive than custom values. If crystals are used in series circuits, load capacitance is not applicable. Load capacitance of parallel circuits is a requirement. 12-MHz Crystals: Frequency Tolerance: Operating Temperature Range: Frequency: Frequency Drift over Temperature: ESR (Series Resistance): Load Capacitance: Shunt Capacitance: Drive Level: Operating Mode: 100 ppm or better 0C to 70C 12 MHz 50 ppm 60 10 pF min. 7 pF max. 0.1-0.5 mW fundamental 48-MHz Crystals: Frequency Tolerance: Operating Temperature Range: Frequency: Frequency Drift over Temperature: ESR (Series Resistance): Load Capacitance: Shunt Capacitance: Drive Level: Operating Mode: 100 ppm or better 0C to 70C 48 MHz 50 ppm 40 10 pF min. 7 pF max. 0.1-0.5 mW third overtone 4.8 USB Transceiver The SL811HS has a built in transceiver that meets USB Specification 1.1. The transceiver is capable of transmitting and receiving serial data at USB full speed (12 Mbits) and low speed (1.5 Mbits). The driver portion of the transceiver is differential while the receiver section is comprised of a differential receiver and two single-ended receivers. Internally, the transceiver interfaces to the Serial Interface Engine (SIE) logic. Externally, the transceiver connects to the physical layer of the USB. 5.0 SL811HS Registers Operation of the SL811HS is controlled through 16 internal registers. A portion of the internal RAM is devoted to the control register space, and access is through the microprocessor interface. The registers provide control and status information for transactions on the USB, microprocessor interface, and interrupts. Any Write to control register 0FH will enable the SL811HS full features bit. This is an internal bit of the SL811HS that enables additional features not supported by the SL11H. For SL11H hardware backward compatibility, this register should not be accessed. The table below shows the memory map and register mapping of both the SL11H and SL811HS. The SL11H is shown for users upgrading to the SL811HS. Document #: 38-08008 Rev. *A Page 8 of 29 SL811HS SL11H (hex) Address 00H 01H 02H 03H 04H 05H 06H Reserved Reserved Reserved Reserved Reserved Reserved 0DH 0EH Reserved 10H-FFH SL811HS (hex) Address 00H 01H 02H 03H 04H 05H 06 H Reserved 08H 09H 0AH 0BH 0CH 0DH 0E H 0F H 10H-FFH Register Name SL11H and SL811HS USB-A Host Control Register USB-A Host Base Address USB-A Host Base Length USB-A Host PID, Device Endpoint (Write)/USB Status (Read) USB-A Host Device Address (Write)/Transfer Count (Read) Control Register1 Interrupt Enable Register Reserved Register USB-B Host Control Register USB-B Host Base Address USB-B Host Base Length USB-B Host PID, Device Endpoint (Write)/USB Status (Read) USB-B Host Device Address (Write)/Transfer Count (Read) Status Register SOF Counter LOW (Write)/HW Revision Register (Read) SOF Counter HIGH and Control Register2 Memory Buffer The registers in the SL811HS are divided into two major groups. The first group is referred to as USB Control registers. These registers enable and provide status for control of USB transactions and data flow. The second group of registers provides control and status for all other operations. 5.1 Register Values on Power-up and Reset The following registers initialize to zero on power-up and reset: * USB-A/USB-B Host Control Register [00H, 08H] bit 0 only * Control Register 1 [05H] * USB Address Register [07H] * Current Data Set/Hardware Revision/SOF Counter LOW Register [0EH] All other registers power-up and reset in an unknown state and should be initialized by firmware. 5.2 USB Control Registers Communication and data flow on the USB uses the SL811HS's USB A-B Control Registers. The SL811HS can communicate with any USB Device functions and any specific endpoints via the USBA or USBB register sets. The USB A-B Host Control Registers can be used in a Ping-Pong arrangement to manage traffic on the USB. The USB Host Control Register also provides a means to interrupt an external CPU or Micro Controller when one of the USB protocol transactions is completed. The table above shows the two sets of USB Host Control Registers, the "A" set and "B" set. The two register sets allow for overlapped operation. When one set of parameters is being set up, the other is transferring. On completion of a transfer to an endpoint, the next operation will be controlled by the other register set. Note. On the SL11H, the USB-B set control registers are not used. The USB-B register set can be used only when SL811HS mode is enabled by initializing register 0FH. The SL811HS USB Host Control has two groups of five registers each, which map in the SL811HS memory space. These registers are defined in the following tables. Document #: 38-08008 Rev. *A Page 9 of 29 SL811HS 5.2.1 SL811HS Host Control Registers Register Name SL11H and SL811H USB-A Host Control Register USB-A Host Base Address USB-A Host Base Length USB-A Host PID, Device Endpoint (Write)/USB Status (Read) USB-A Host Device Address (Write)/Transfer Count (Read) USB-B Host Control Register USB-B Host Base Address USB-B Host Base Length USB-B Host PID, Device Endpoint (Write)/USB Status (Read) USB-B Host Device Address (Write)/Transfer Count (Read) 5.2.2 USB-A/USB-B Host Control Registers [00H, 08H] Bit Name Arm Enable Direction Reserved ISO SOF Data Toggle Bit Preamble When set to "1" allows Isochronous mode for this endpoint. "1" = Synchronize with the SOF transfer "0" if DATA0, "1" if DATA1. If set = "1" a preamble token is transmitted prior to transfer of low-speed packet. If set = "0," preamble generation is disabled. Function Allows enabled transfers when set = "1." Cleared to "0" when transfer is complete. When set = "1" allows transfers to this endpoint. When set "0" USB transactions are ignored. If Enable = "1" and Arm = '0' the endpoint will return NAKs to USB transmissions. When set = "1" transmit to Host. When "0" receive from Host. SL11H (hex) Address 00H 01H 02H 03H 04H Reserved Reserved Reserved Reserved Reserved SL811HS (hex) Address 00H 01H 02H 03H 04H 08H 09H 0AH 0BH 0CH Bit Position 0 1 2 3 4 5 6 7 * Bit 3 is reserved for future usage. * The SL811HS uses bit 5 to enable transfer of a data packet after a SOF packet is transmitted. When this bit set "1," the next enabled packet will be sent after next SOF. If set = "0" the next packet is sent immediately if the SIE is free. * The SL811HS automatically generates preamble packets when bit 7 is set. This bit is only used to send packets to a low-speed device through a hub. To communicate to a full speed device, this bit is set to zero. For example, when SL811HS communicates to a low-speed device via the HUB: -- SL811HS SIE should set to operate at 48 MHz, i.e., bit 5 of register 05H should be set = "0." -- Bit 6 of register 0FH should be set = "0," set correct polarity of DATA+ and DATA- state for Full Speed. -- Bit 7, Preamble Bit, should be set = "1" in Host Control register. * When SL811HS communicates directly to low-speed device: -- SL811HS. Bit 5 of register 05H should be set = "1." -- Bit 6 of register 0FH should be set = "1," DATA+ and DATA- polarity for low speed. -- The state of bit 7 is ignored in this mode. 5.2.3 Example of SL811HS USB Packet Transfer SL811HS memory set-up as shown: 03h-04h Register will contain PID and Device endpoint and Device Address. 10h-FFh USB Data as required. Document #: 38-08008 Rev. *A Page 10 of 29 SL811HS 5.2.4 SOF Packet Generation The SL811HS automatically computes CRC5 by hardware. No CRC or SOF is required to be generated by external firmware for SL811HS. 5.2.5 USB-A/USB-B Host Base Address [01H, 09H] The USB-A/USB-B Base Address is a Pointer to the SL811HS memory buffer location for USB reads and writes. When transferring data OUT (Host to Device), the USB-A and USB-B can be set up prior to setting ARM on the USB-A or USB-B Host Control register. See the software implementation example. 5.2.6 USB-A/USB-B Host Base Length [02H, 0AH] The USB A/B host base register contains the maximum packet size to be transferred between the SL811HS and a slave USB peripheral. Essentially, this designates the largest packet size that can be transferred by the SL811HS. Base Length designates the size of data packet to be sent. For example, in Bulk mode the maximum packet length is 64 bytes. In ISO mode, the maximum packet length is 1023, since the SL811HS only has an 8-bit length; the maximum packet size for the ISO mode using the SL811HS is 255 - 16 bytes. When the Host Base Length register is set to zero, a Zero-Length packet will be transferred. 5.2.7 USB-A/USB-B Host PID, Device Endpoint (Write)/USB Status (Read) [03H, 0BH] This register has two modes. When read, this register provides packet status and it contains information relative to the last packet that has been received or transmitted. The register is defined as follows. Bit Position 0 1 2 3 4 5 6 7 Bit Name ACK Error Time-out Sequence Setup Overflow NAK STALL Transmission Acknowledge Error detected in transmission Time-out occurred Sequence Bit. "0" if DATA0, "1" if DATA1 "1" indicates Setup Packet Overflow condition - maximum length exceeded during receives Slave returns NAK Slave set STALL bit Function When written, this register provides the PID and Endpoint information to the USB SIE engine to be used in the next transaction. All sixteen Endpoints can be addressed by the SL811HS. D7 PID3 PID3-0 EP3-0 D6 PID2 D5 PID1 D4 PID0 D3 EP3 D2 EP2 D1 EP1 D0 EP0 4-bit PID Field (See Table Below) 4-bit Endpoint Value in Binary. PID TYPE SETUP IN OUT SOF PREAMBLE NAK STALL DATA0 DATA1 D7-D4 1101 (D Hex) 1001 (9 Hex) 0001 (1 Hex) 0101 (5 Hex) 1100 (C Hex) 1010 (A Hex) 1110 (E Hex) 0011 (3 Hex) 1011 (B Hex) Document #: 38-08008 Rev. *A Page 11 of 29 SL811HS 5.2.8 USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [04H, 0CH] This register has two functions. When read, this register contains the number of bytes left over (from "Length" field) after a packet is transferred. If an overflow condition occurs, i.e., the received packet from slave USB device was greater than the Length field specified, a bit is set in the Packet Status Register indicating the condition. When written, this register will contain the USB Device Address to which the Host wishes to communicate. D7 0 D6 DA6 DA6-DA0 DA7 D5 DA5 D4 DA4 D3 DA3 D2 DA2 D1 DA1 D0 DA0 Device address, up to 127 devices can be addressed Reserved bit should be set zero. 5.3 SL811HS Control Registers Register Name SL11H and SL811H SL11H (hex) Address 05H 06H 07H 0DH 0EH Reserved 10H-FFH SL811HS (hex) Address 05H 06 H 07 H 0DH 0E H 0F H 10H-FFH Control Register1 Interrupt Enable Register Reserved Register Status Register SOF Counter LOW (Write)/HW Revision Register (Read) SOF Counter HIGH and Control Register2 Memory Buffer 5.3.1 Control Register 1, Address [05H] The Control Register 05H enables/disables USB transfer operation with control bits defined as follows. Bit 0 1 2 3 4 5 6 7 Bit Name SOF ena/dis Reserved Reserved USB Engine Reset J-K state force USB Speed Suspend Reserved USB Engine reset = "1." Normal set "0" See the table below "0" set-up for full speed, "1" set-up LOW-SPEED "1" enable, "0" = disable Function "1" enable auto Hardware SOF generation, "0"= disable * At power-up this register will be cleared to all zeros. * In the SL811HS, bit 0 is used to enable HW SOF auto-generation (bit 0 was not used in the SL11H). Document #: 38-08008 Rev. *A Page 12 of 29 SL811HS 5.3.2 J-K Programming States [bits 3 and 4 of Control Register 05H] The J-K force state control and USB Engine Reset bits can be used to generate USB reset condition on the USB. Forcing K-state can be used for Peripheral device remote wake-up, Resume and other modes. These two bits are set to zero on power-up. Bit 4 0 0 1 1 5.3.3 Bit 3 0 1 0 1 Normal operating mode Force USB Reset, D+ and D- are set LOW (SE0) Force J-State, D+ set HIGH, D- set LOW[2] Force K-State, D- set HIGH, D+ set LOW[3] Function Low-speed/Full Speed Modes [bit 5 Control Register 05H] The SL811HS is designed to communicate with either full or low-speed devices. At power-up bit 5 will be set LOW, i.e., for full speed. There are two cases when communicating with a low-speed device. When a low-speed device is connected directly to the SL811HS, bit 5 of Register 05H should be set to logic "1" and bit 6 of register 0FH, Output-Invert, needs to be set to "1" in order to change the polarity of D+ and D-. When a low-speed device is connected via a HUB to SL811HS, bit 5 of Register 05H should be set to logic "0" and bit 6 of register 0FH should be set to logic "0" in order to keep the polarity of D+ and D- for full speed. In addition, make sure that bit 7 of USB-A/USB-B Host Control Registers [00H, 08H] is set to "1." 5.3.4 Low-power Modes [bit 6 Control Register 05H] When bit-6 (Suspend) is set to "1," the power of the transmit transceiver will be turned off, the internal RAM will be in the suspend mode, and the internal clocks will be disabled. Note. Any activity on the USB bus (i.e., K-State, etc.) will resume normal operation. To resume normal operation from the CPU side, a data Write cycle (i.e., A0 set HIGH for a data Write cycle) should be done. 5.3.5 Interrupt Enable Register, Address [06H] The SL811HS provides an Interrupt Request Output, which can be activated on a number of conditions. The Interrupt Enable Register allows the user to select conditions that will result in an Interrupt being issued to an external CPU. A separate Interrupt Status Register is provided. It can be polled in order to determine those conditions that initiated the interrupt. (See Interrupt Status Register description.) When a bit is set to "1" the corresponding interrupt is enabled. Bit Position 0 1 2 3 4 5 6 Bit Name USB-A USB-B Reserved Reserved SOF Timer Inserted/Removed Device Detect/Resume 1 = Enable Interrupt on 1-ms SOF Timer Slave Insert/Remove Detection Enable Device Detect/Resume Interrupt USB-A Done Interrupt USB-B Done Interrupt Function * Bits 0-1 are used for the USB A/B controller interrupt. * Bit 4 is used to enable/disable the SOF timer. To utilize this bit function, bit 0 of register 05H must be enabled and the SOF counter registers 0EH and 0FH must be initialized. * Bit 5 is used to enable/disable the device inserted/removed interrupt. * When bit-6 of register 05H is set = "1," bit 6 of this register enables the Resume Detect Interrupt. Otherwise, this bit is used to enable Device detection status as defined in the Interrupt Status Register bit definitions. Note: 2. Force K-State for low speed. 3. Force J-State for low speed. Document #: 38-08008 Rev. *A Page 13 of 29 SL811HS 5.3.6 USB Address Register, Reserved, Address [07H] This register is reserved for the device USB Address in Slave operation. It should not be written by the user. 5.3.7 Interrupt Status Register, Address [0DH] The ISR is a Read/Write register providing interrupt status. Interrupts can be cleared by writing to this register. To clear a specific interrupt, the register is written with corresponding bit set to "1." Bit Position 0 1 2 3 4 5 6 7 Bit Name USB-A USB-B Reserved Reserved SOF timer Insert/Remove Device Detect/Resume D+ 1 = Interrupt on 1-ms SOF Timer Slave Insert/Remove Detection Device Detect/Resume Interrupt Value of the Data+ Pin USB-A Done Interrupt USB-B Done Interrupt Function * Bit 5 is provided to support USB cable Insertion/Removal for the SL811HS in Host Mode. This bit is set when a transition from SE0 to IDLE (device inserted) or IDLE to SE0 (device removed) occurs on the bus. * Bit 6 is shared between Device Detection status and Resume detection interrupt. When bit-6 of register 05H is set to one, this bit will be the Resume detection Interrupt bit. Otherwise, this bit is used to indicate the presence of a Device, "1" = device "Not present" and "0" = device "Present." In this mode this bit should be checked along with bit 5 to determine whether a device has been inserted or removed. * Bit 7 provides continuous USB Data+ line status. Once it has been determined that a device has been inserted as described above with bits 5 and 6, bit 7 can be used to detect if the inserted device is low- or full-speed. 5.3.8 Current Data Set Register/Hardware Revision/SOF Counter LOW, Address [0EH] * This register has two modes: a Read from this register indicates the current SL811HS silicon revision. Bit Position 0 1 2 3 4-7 Bit Name Reserved Reserved Reserved Reserved HW Revision Reserved for slave Reserved for slave Read will be zero Read will be zero SL11H Read = 0H, SL811HS rev1.2 Read = 1H, SL811HS rev1.5 Read = 2 Function * Writing to this register will set up auto generation of SOF to all connected peripherals. This counter is based on the 12-MHz clock. To set up a 1-ms timer interval, the software must set up both SOF counter registers to the proper values. Bit Position 0-7 Bit Name SOF LOW Counter Register Function Write-only to set SOF LOW Counter Register, OEH * Example. To set up SOF for 1-ms interval, SOF counter register 0EH should be set to E0H. Document #: 38-08008 Rev. *A Page 14 of 29 SL811HS 5.3.9 SOF Counter HIGH/Control2 Register, Address [0FH, READ/WRITE] When writing to this register the bits definition are defined as follows. Bit Position 0-5 6 7 Bit Name SOF HIGH Counter Register SL811HS D+/D- Data Polarity Swap SL811HS Master/Slave selection Function Write a value or read it back to SOF HIGH Counter Register Write/Read, set "1" change polarity, "0" no change of polarity Write/Read, "1" is master, else Slave Note. Any Write to control register 0FH will enable the SL811HS full features bit. This is an internal bit of the SL811HS which enables additional features not supported by the SL11H. For SL11H hardware backward compatibility, this register should not be accessed. The USB-B register set can be used when SL811HS full feature bit is enabled. Example. To set up for 1-ms SOF time: The register 0FH contains the upper 6 bits of the SOF timer. Register 0EH contains the lower 8 bits of the SOF timer. The timer is based on a 12-MHz clock and uses a counter, which counts down to zero from an initial value. To set the timer for 1 ms time, the register 0EH should be loaded with value E0H, register 0F, Bits 0-5 should be loaded with 2EH. To start the timer, bit 0 of register 05H should be set to "1." To load both HIGH and LOW registers with the proper values the user must follow this sequence: -- Write E0H to register 0EH. -- Write 2EH to register 0FH, bits 0-5. Bits 6 and 7 should be set for appropriate function: polarity and Master/Slave. -- Enable bit 0 in register 05H. Note. Any Write to the 0FH register will clear the internal frame counter. Register 0FH must be written at least once after power-up. The internal frame counter is incremented after every SOF timer tick. The internal frame counter is an 11-bit counter, which is used to track the frame number. The frame number is incremented after each timer tick. Its contents are transmitted to the slave every millisecond in a SOF packet. D7 C13 D6 C12 C13-C6 D5 C11 D4 C10 D3 C9 D2 C8 D1 C7 D0 C6 Top 8 bits of 14-bit SOF counter. When read, this register will return the value of the SOF counter divided by 64. The software should use this register to determine the available bandwidth in the current frame before initiating any USB transfer. In this way, the user will be able to avoid babble conditions on the USB. For example, to determine the available bandwidth left in a frame: Maximum number of clock ticks in 1-ms time frame is 12000(1 count per 12-MHz clock period, or approximately 84 ns.) The value read back in Register 0FH is the (count x 64) x 84 ns = time remaining in current frame. USB bit time = one 12-MHz period. Value of register 0FH BBH BAH Available bit times left are between 12000 bits to 11968 (187 x 64) bits 11968 bits to 11904 (186 x 64) bits Document #: 38-08008 Rev. *A Page 15 of 29 SL811HS 6.0 SL811HS and SL811HST-AC Physical Connections This part is offered in both a 28-pin PLCC package (SL811HS) and a 48-pin TQFP package (SL811HST-AC). 6.1 6.1.1 SL811HS Physical Connections SL811HS Pin Layout nRD N C* NC* A0 VDD1 M/S D7 26 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2 1 28 27 25 24 23 D6 D5 D4 G nd D3 D2 D1 Pins 2 and 3 should be No Connect in Host Mode. See Pin and Signal Description. 4 nW R nCS CM VDD2 DATA + DATA G nd SL811HSH 28 PLCC 22 21 20 19 VDD 1 CLK/X 1 X2 nRST INTR Q G nd D0 Figure 6-1. SL811HS USB Host/Slave Controller--Pin Layout 6.1.2 28-Pin PLCC Mechanical Dimensions Document #: 38-08008 Rev. *A Page 16 of 29 SL811HS 6.1.3 SL811HS USB Host Controller Pins Description The SL811HS package is a 28-pin PLCC. The device requires 3.3 VDC. Average typical current consumption is less then 20 mA for 3.3V. Table 6-1. SL811HS Pin Assignments and Definitions Pin No. 1 2 Pin Type IN IN Pin Name A0 nDACK Pin Description A0 = "0." Selects Address Pointer. Reg. Write Only. Selects Data Buffer or Register. R/W.[4] DMA Acknowledge. An active LOW input used to interface to an external DMA controller. This works only in slave mode. In host mode, pin should be tied to Logic "1" in Host Mode. DMA Request. An active LOW output used with an external DMA controller. nDRQ and nDACK form the handshake for DMA data transfers. In host mode, pin must be left unconnected in Host Mode. Read Strobe Input. An active LOW input used with nCS to Read registers/data memory. Write Strobe Input. An active LOW input used with nCS to Write to registers/data memory. Active LOW Chip Select. Used with nRD and nWD when accessing SL811HS. Clock Mode. Select Internal 4 X Clock Multiplier. "1" enables 4X clock multiplier. "0" Disables.[5] Power for USB Transceivers USB Differential Data Signal HIGH Side USB Differential Data Signal LOW Side Ground Connection for USB SL811HS Device VDD Power[6] 12-/48-MHz Clock or External Crystal X1 Connection[7] External Crystal X2 Connection SL811HS Device Active LOW Reset Input Active HIGH Interrupt Request Output to External Controller SL811HS Device Ground Data 0. Microprocessor Data/(Address) Bus Data 1. Microprocessor Data/(Address) Bus Data 2. Microprocessor Data/(Address) Bus Data 3. Microprocessor Data/(Address) Bus SL811HS Device Ground Data 4. Microprocessor Data/(Address) Bus Data 5. Microprocessor Data/(Address) Bus Data 6. Microprocessor Data/(Address) Bus Data 7. Microprocessor Data/(Address) Bus Master/Slave Select. Host = "0," Slave = "1" SL811HS Device VDD Power 3 OUT nDRQ 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 IN IN IN IN VDD1 BIDIR BIDIR GND VDD IN OUT IN OUT GND BIDIR BIDIR BIDIR BIDIR GND BIDIR BIDIR BIDIR BIDIR IN VDD nRD nWR nCS CM +3.3 VDC DATA + DATA USB GND +3.3 VDC CLK/X1 X2 nRST INTRQ GND D0 D1 D2 D3 GND D4 D5 D6 D7 M/S +3.3 VDC Notes: 4. The A0 Address bit is used to access address or data registers in I/O-mapped or memory-mapped applications. 5. The CM Clock Multiplier pin should be tied HIGH for a 12-MHz clock source and tied to ground for a 48-MHz clock source. In SL11H, this pin was designated as an ALE input pin. 6. VDD can be derived from the USB supply. The diagram below shows a simple method to provide 3.3V/30 mA. Another option is to use a Torex Semiconductor, Ltd. 3.3V SMD regulator (part number XC62HR3302MR). 7. The X1/X2 clock requires external 12- or 48-MHz matching crystal or clock source. Document #: 38-08008 Rev. *A Page 17 of 29 SL811HS The Diagram below illustrates a simple +3.3V voltage source. $WAV T7A S A #$APu A !I !!!! a rr A Y 1&7 B I 9A 9 9'' 6DP SOH 9'' *HQHUDWRU 6.1.4 Package Markings (SL811HS) YYWW = Date code XXXX = Product code X.X = Silicon revision number Document #: 38-08008 Rev. *A Page 18 of 29 SL811HS 6.2 6.2.1 SL811HST-AC Physical Connections SL811HST-AC Pin Layout NC NC 1 NC NC nWR nCS CM VDD1 Data+ DataUSBGnd NC NC NC 13 NC NC nRST GND Clk/X1 VDD D0 INTRQ X2 NC NC NC 48 36 NC NC [16] nRD NC NC NC A0 VDD D7 M/SDD NC NC 37 NC D6 D5 SL811HST D4 GND D3 D2 D1 NC 12 24 25 NC Figure 6-2. SL811HST-AC USB Host/Slave Controller Pin Layout 6.2.2 Mechanical Dimensions 48-Pin TQFP Note: 8. NC. Indicates No Connection. NC Pins should be left unconnected. Document #: 38-08008 Rev. *A Page 19 of 29 SL811HS 6.2.3 SL811HST-AC USB Host Controller Pins Description The SL811HST-AC is packaged in a 48-pin TQFP. The device requires a 3.3VDC power source. The SL811HST-AC requires an external 12 or 48 MHz crystal or Clock. Table 6-2. SL811HST-AC Pin Assignments and Definitions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Type NC NC IN IN IN VDD1 BIDIR BIDIR GND NC NC NC NC NC VDD IN OUT IN OUT GND BIDIR NC NC NC NC NC BIDIR BIDIR BIDIR GND BIDIR BIDIR Pin Name NC NC nWR nCS CM +3.3 VDC DATA + DATA USB GND NC NC NC NC NC +3.3 VDC CLK/X1 X2 NRST INTRQ GND D0 NC NC NC NC NC D1 D2 D3 GND D4 D5 NC NC Write Strobe Input. An active LOW input used with nCS to Write to registers/data memory. Active LOW SL811HST-AC Chip select. Used with nRD and nWr when accessing SL811HT. Clock Mode. Select 12-MHz/48-MHz Clock Source.[9] Power for USB Transceivers. VDD1 may be connected to VDD. USB Differential Data Signal HIGH Side USB Differential Data Signal LOW Side Ground Connection for USB NC NC NC NC NC SL811HST-AC Device VDD Power[10] Clock or External Crystal X1 connection[11] External Crystal X2 connection SL811HST-AC Device active low reset input Active HIGH Interrupt Request output to external controller SL811HST-AC Device Ground Data 0. Microprocessor Data/(Address) Bus. NC NC NC NC NC Data 1. Microprocessor Data/(Address) Bus. Data 2. Microprocessor Data/(Address) Bus. Data 3. Microprocessor Data/(Address) Bus. SL811HST-AC Device Ground Data 4. Microprocessor Data/(Address) Bus. Data 5. Microprocessor Data/(Address) Bus. Pin Description Notes: 9. The CM Clock Multiplier pin should be tied HIGH for a 12-MHz clock source and tied to ground for a 48-MHz clock source. In SL11H, this pin was designated as ALE input pin. 10. VDD can be derived from the USB supply. See diagram. 11. The X1/X2 Clock requires external 12- or 48-MHz matching crystal or clock source. Document #: 38-08008 Rev. *A Page 20 of 29 SL811HS Table 6-2. SL811HST-AC Pin Assignments and Definitions (continued) Pin No. 33 34 35 36 37 38 39 40 41 42 43 Pin Type BIDIR NC NC NC NC NC BIDIR IN VDD IN IN Pin Name D6 NC NC NC NC NC D7 M/S +3.3 VDC A0 nDACK Pin Description Data 6. Microprocessor Data/(Address) Bus. NC NC NC NC NC Data 7. Microprocessor Data/(Address) Bus. Master/Slave Mode Select. "1" selects Slave. "0" = Master. SL811HST-AC Device VDD Power. A0 = "0." Selects address pointer. Reg.A0 = "1." Selects data buffer or register.[12] DMA Acknowledge. An active LOW input used to interface to an external DMA controller. DMA is enabled only in slave mode. In host mode, pin should be tied HIGH (logic "1") . DMA Request. An active LOW output used with an external DMA controller. nDRQ and nDACK form the handshake for DMA data transfers. In host mode, pin must be left unconnected . Read Strobe Input. An active LOW input used with nCS to Read registers/data memory. NC NC NC 44 OUT nDRQ 45 46 47 48 IN NC NC NC NRD NC NC NC Notes: 12. The A0 Address bit is used to access address register or data registers in I/O Mapped or Memory Mapped applications. 6.2.4 Package Markings (SL811HST-AC) SL811HST YYWW-X.X XXXX YYWW = Date code XXXX = Product code X.X = Silicon revision number Document #: 38-08008 Rev. *A Page 21 of 29 SL811HS 7.0 7.1 Electrical Specifications Absolute Maximum Ratings This section lists the absolute maximum ratings of the SL811HS. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability. Storage Temperature Voltage on any pin with respect to ground Power Supply Voltage (VDD) Power Supply Voltage (VDD1) Lead Temperature (10 seconds) -40C to 125C -0.3V to 6.0V 4.0 V 4.0 V 180C 7.2 Recommended Operating Condition Parameter Min. 3.0V 3.0V 0C Typical 3.3 V Max. 3.45V 3.45V 65C Power Supply Voltage, VDD Power Supply Voltage, VDD1 Operating Temperature Crystal Requirements, (X1, X2) Operating Temperature Range Parallel Resonant Frequency [13] Min. 0C Typical Max. 65C 48 MHz 50 ppm 30 ppm 100 ohms 3 pF 20 pF 20 W [14] Frequency Drift over Temperature Accuracy of Adjustment Series Resistance Shunt Capacitance Load Capacitance Drive Level Mode of Vibration Third Overtone 6 pF 5 mW 7.3 External Clock Input Characteristics (X1) Parameter Min. 1.5 V 48 MHz Typical Max. Clock Input Voltage @ X1 (X2 Open) Clock Frequency [15] Notes: 13. The SL811HS can use a 12-MHz Crystal Oscillator or 12-MHz Clock Source. 14. Fundamental mode for 12-MHz Crystal. 15. The SL811HS can use a 12-MHz Clock Source. Document #: 38-08008 Rev. *A Page 22 of 29 SL811HS 7.4 DC Characteristics Description Input Voltage LOW Input Voltage HIGH (5V Tolerant I/O) Output Voltage LOW (IOL = 4 mA) Output Voltage HIGH (IOH = -4 mA) Output Current HIGH Output Current LOW Input Leakage Input Capacitance Supply Current (VDD) inc USB @FS Supply Current (VDD) Suspend w/Clk & Pll Enb Supply Current (VDD) Suspend no Clk & Pll Dis Supply Current (VDD1) Transceiver Supply Current in Suspend 21 mA 4.2 mA 50 A [16] Parameter VIL VIH VOL VOH IOH IOL ILL CIN ICC ICCsus1[17] ICCsus2[18] IUSB IUSBSUS Min. -0.3 V 2.0 V Typ. Max. 0.8V 6.0V 0.4V 2.4 V 4 mA 4 mA 1 A 10 pF 25 mA 5 mA 60 A 10 mA 10 A 7.5 USB Host Transceiver Characteristics Parameter Description Differential Input Sensitivity (Data+, Data-) USB Input Voltage HIGH Driven USB Input Voltage LOW USB Output Voltage HIGH USB Output Voltage LOW Output Impedance HIGH STATE Output Impedance LOW STATE Transceiver Supply p-p Current (3.3V) Min. 0.2V 2.0 0.8V 2.0V 0.0V 36 Ohms 36 Ohms 0.3 V 42 Ohms 42 Ohms 10 mA @ FS Typ.[19] Max. 200 mV VIHYS VUSBIH VUSBIL VUSBOH VUSBOL ZUSBH[20] ZUSBL[20] IUSB Every VDD pin, including USB VDD, has to have a decoupling capacitor to ensure clean VDD (free of high-frequency noise) at the chip input point (pin) itself. The best way to do this is to connect a ceramic capacitor (0.1 F, 6V) between the pin itself and a good ground. Capacitor leads must be kept as short as possible. Use surface mount capacitors with the shortest traces possible (the use of a ground plane is strongly recommended). Notes: 16. ICC measurement includes USB Transceiver current (IUSB) operating at Full Speed. 17. ICCsus1 measured with 12-MHz Clock Input and Internal PLL enabled. Suspend set -(USB transceiver and internal Clocking disabled). 18. ICCsus2 measured with external Clock, PLL disabled, and Suspend set. For absolute minimum current consumption, ensure that all inputs to the device are at static logic level. 19. All typical values are VDD = 3.3V and TAMB= 25C. 20. =86%; impedance values includes an external resistor of 24 Ohms 1% (SL811HS revision 1.2 requires external resistor values of 33 Ohms 1%). Document #: 38-08008 Rev. *A Page 23 of 29 SL811HS 7.6 7.6.1 Bus Interface Timing Requirements I/O Write Cycle twr twrhigh nWR twasu twahld twdsu A0 twdsu twdhld Register or Memory Address twcsu twshld twdhld D0-D7 DATA nCS Tcscs See Note. I/O Write Cycle to Register or Memory Buffer Note: nCS an be held LOW for multiple Write cycles provided nWR is cycled. Parameter tWR tWCSU tWSHLD tWASU tWAHLD tWDSU tWDHLD tCSCS tWRHIGH Description Write pulse width Chip select set-up to nWR LOW Chip select hold time After nWR HIGH A0 address set-up time A0 address hold time Data to Write HIGH set-up time Data hold time after Write HIGH nCS inactive to nCS* asserted NWR HIGH Min. 65 ns 0 ns 0 ns 65 ns 10 ns 60 ns 5 ns 85 ns 85 ns Typ. Max. Write Cycle Time for Auto Inc Mode Writes is 150 ns minimum. Document #: 38-08008 Rev. *A Page 24 of 29 SL811HS 7.6.2 I/O Read Cycle twr twrrdl nWR twasu twahld A0 trdp nRD twdsu twdhld Register or Memory Address trcsu tracc trdhld D0-D7 DATA trshld nCS Tcscs *Note I/O Read Cycle from Register or Memory Buffer Parameter tWR tRD tWCSU tWASU tWAHLD tWDSU tWDHLD tRACC tRDHLD tRCSU tRSHLD TCSCS* tWRRDL Write pulse width Read pulse width Chip select set-up to nWR A0 address set-up time A0 address hold time Data to Write HIGH set-up time Data hold time after Write HIGH Data valid after Read LOW Data hold after Read HIGH Chip select LOW to Read LOW NCS hold after Read HIGH nCS inactive to nCS *asserted nWR HIGH to nRD LOW Description Min. 65 ns 65 ns 0 ns 65 ns 10 ns 60 ns 5 ns 20 ns 5 ns 0 ns 0 ns 85 ns 85ns 25 ns Typ. Max. Note. NCS can be kept LOW during multiple Read cycles provided nRD is cycled. Rd Cycle Time for Auto Inc Mode Reads is 150 ns minimum. Document #: 38-08008 Rev. *A Page 25 of 29 SL811HS 7.6.3 Reset Timing treset nRST tioact nRD or nWR RESET TIMING Parameter tRESET tIOACT Description nRst Pulse width nRst HIGH to nRD or nWR active Min. 16 clocks 16 clocks Typ. Max. Note. Clock is 48-MHz nominal. Document #: 38-08008 Rev. *A Page 26 of 29 SL811HS 7.6.4 Clock Timing Specifications tclk CLK thigh tlow tfall trise CLOCK TIMING Parameter tCLK tHIGH tLOW tRISE tFALL Description Clock Period (48 MHz) Clock HIGH Time Clock LOW Time Clock rise Time Clock fall Time Clock Duty Cycle Min. 20.0 ns 9 ns 9 ns Typ. 20.8 ns Max. 11 ns 11 ns 5.0 ns 5.0 ns 45% 55% Document #: 38-08008 Rev. *A Page 27 of 29 SL811HS 8.0 Package Diagrams 28-pin PLCC 48-pin TQFP Intel is a registered trademark of Intel Corporation. Torex is a trademark of Torex Semiconductors, Ltd. SL811HS is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-08008 Rev. *A Page 28 of 29 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. SL811HS Document Title: SL811HS USB Host/Slave Controllers Hardware Specification Document Number: 38-08008 REV. ** *A ECN NO. 110850 112687 Issue Date 12/14/01 03/22/02 Orig. of Change BHA MUL Description of Change Converted to Cypress format from ScanLogic 1) Changed power supply voltage to 4.0V in section 7.1 2) Changed value of twdsu in section 7.6.2 3) Changed max. power supply voltage to 3.45 V in section 7.2 4) Changed accuracy of adjustment in section 7.2 5) Changed bits 0 and 1 to reserved in section 5.3.8 6) Changed bit 2 to reserved in section 5.3.5 and 5.3.7 7) Changed bit 2 to reserved in section 5.3.1 8) Changed definition of bit 6 in section 5.3.5 & 5.3.7 9) Added section 5.1, Register Values on Power-up and Reset 10) Changed bit description notes in section 5.3.7 11) Changed note about series termination resistors in section 7.5 12) Changed example in section 5.3.9 13) Changed J-K Programming States table in section 5.3.2 14) Added and removed comments for low-power modes in section 5.3.4 15) Removed sections specific to slave operation and SL11H 16) Removed duplicate tables 17) General formatting changes to section headings 18) Fixed all part number references 19) Added comments to section 7.5 and new definitions to section 2.0 Document #: 38-08008 Rev. *A Page 29 of 29 |
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